Many electronic devices use a Pulse Width Modulation (PWM) signal to control or regulate their outputs. A PWM signal can be modulated by varying the signal frequency and/or duty ratio. This kind modulation often uses complicated algorithms and often requires sophisticated circuits that can take up significant real estate on a device chip.
Dual phase electronic devices share a given PWM period that is divided into two phases. According to the design purpose, the divided time could be overlapped or non-overlapped. For example, in case of a (half) bridge converter certain switches must be non-overlapped to prevent an undesired short-through between upper and the lower switches. An LLC converter has a half bridge configuration on the primary side and the upper and lower switches share its switching period evenly. That is, each switch has a 50% duty ratio to its switching period. Also, the twin rectifiers, e.g., Schottky diodes or Synchronous Rectifiers, on the secondary side of an LLC converter follow the primary switching frequency and commutate in an alternating fashion while their operation time is the same each other.
However, when switches turn-on or turn-off there is a turn-on or turn-off delay, which may include a rising or falling time and propagation delay. Thus, if the switches have the same 50% duty ratio the secondary rectifiers cannot help turning on at once in a short time during commutating. Therefore, their each maximum duty ratio should be less than 50%.
In circuits for which a secondary side rectifier synchronizes with a primary side circuit and receives period and duty information from the primary side it is not difficult to modulate the on/off switching of the primary and secondary sides. However, if the secondary side cannot get duty information from the primary side, duty ratio modulation is necessary because the secondary side rectifier switch can never know when the primary side rectifier switch turns on or off Therefore, in order to ensure enough dead time to avoid turning both switches on at the same time it is necessary to monitor the PWM frequency and duty information and generate a proper turn-on time.
Examples of circuits for which the secondary cannot receive duty information from the primary include flyback circuits commonly used in low power applications (less than 100 W). For higher power applications, e.g., 100-200 W, an LLC circuit may be used, e.g., in a switching mode power supply (SMPS) for television, monitor, personal computers, and the like. In the case of an LLC circuit, one often needs to know when to turn off a switch in the LLC secondary side. To do this the secondary needs to receive information about the primary side switching frequency and duty ratio. However, because the primary and secondary are isolated by a transformer the secondary cannot receive the primary side switching frequency or the duty ratio without additional application. Also, in an LLC application, the resonant switching frequency has a variation. Furthermore, in most applications, the resonant frequency of an LLC circuit may vary considerably according to operating conditions. In such applications it is quite difficult to add an appropriate delay or lead time against those kinds of variation in the LLC using conventional duty modulation. As used herein, “delay” means that an action is done after an expected event and “lead” means that an action is done before the expected event.
FIG. 1A depicts a conventional duty modulator 100 having a ramp signal generator 102, an amplifier 104 and a comparator 106. The ramp signal generator 102 generates a triangular or sawthooth Vramp waveform based on a clock signal having a clock frequency f as shown in FIG. 1B. The amplifier 104 provides gain to an input signal Vin to generate a comparison signal Vcomp. The comparator compares Vramp to Vcomp and generates an output signal Vout. In this example, Vout goes “high” if Vramp is larger than Vcomp and goes “low” if Vcomp is larger than Vramp.
This type of conventional duty modulator can convert the input voltage signal Vin into time domain duty information. For successful Voltage-Time conversion the clock frequency f should be constant. However, if the clock frequency f used to trigger the ramp signal Vramp is a PWM signal for which the PWM frequency varies the output duty cannot be stable. FIG. 2 illustrates how the duty varies due to frequency change. If the frequency f varies, the Ramp generator generates a ramp signal with different peak heights, e.g., Vpp_l, Vpp_m, Vpp_h, because the slope of the ramp signal Vramp is fixed. However, if the Vcomp level is also fixed, the duty ratio of the output signal Vout changes. It is quite difficult to change the Vcomp level for duty to be constant because converting from frequency to voltage requires additional circuits, such as a phase locked loop (PLL).
It is within this context that aspects of the present disclosure arise.